Sub-layer contact technique using in situ doped amorphous silicon and solid phase recrystallization.

摘要

A method of providing sublayer contacts in vertical walled trenches is proposed. In accordance with the present invention, the phosphorus doped amorphous silicon is deposited at temperatures less than 570 DEG C. The conversion into the extremely large crystal low resistivity polysilicon is accomplished by a low temperature anneal at 400 DEG C to 500 DEG C for several hours and the short RTA treatment at a high temperature approximately 850 DEG C for twenty seconds. These two conversion heat treatments are done at sufficiently thermal budget to prevent any significant dopant movement within a shallow junction transistor. After anneal, the excess low resistivity silicon is planarized away by known techniques such as chemical/mechanical polishing. In addition, due to the trench filling abilities of the amorphous silicon CVD process, in one preferred embodiment of the invention the capability of accessing subsurface silicon layers at different trench depths is demonstrated.