| 摘要 |
PURPOSE:To obtain an emitter follower circuit which can reduce a Circuit layout area together with reduction of the power consumption and furthermore can output a stable binary logical signal together with improvement of the operating speed. CONSTITUTION:An input signal Vin is inputted to the base of an npn transistor Tr1 connected to a high potential power supply Vcc through its collector. A binary logical signal having the same phase as the input signal Vin received from the emitter of the TR1 is outputted as an output signal Vout. The emitter of the Tr1 is connected to a low potential power supply VEE via a load and a current source 1. Thus an emitter follower circuit is obtained. The load of a semiconductor logic circuit where many emitter follower circuits are connected in parallel consists of a MOS Tr2 which is always kept turned on with the gate voltage of a fixed level. |
