发明名称 Precharging circuit of bit line for reading an EPROM memory cell.
摘要 The circuit comprises a transistor (M3) for regulating the drain voltage of the cell (C1) to be read and an inverter (M1, M2) for driving the regulating transistor (M3), having the same drain voltage as input. It also comprises a fast precharge transistor (M6) of the bit line (Bl), that has the gate connected to the gate of the regulating transistor (M3) and the source connected to the drain of the regulating transistor (M3), so that it is quenched by the drain voltage of the regulating transistor (M3) following its rise at the end of the precharge of the bit line (Bl). <IMAGE>
申请公布号 EP0516225(A2) 申请公布日期 1992.12.02
申请号 EP19920201461 申请日期 1992.05.22
申请人 SGS-THOMSON MICROELECTRONICS S.R.L. 发明人 VILLA, CORRADO
分类号 G11C16/06;G11C17/00;G11C16/24 主分类号 G11C16/06
代理机构 代理人
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