发明名称
摘要 PURPOSE:To speed up the processing of the multiplexing controller by transmitting integral arithmetic results of respective controlled systems to respective controllers, judging whether output signals of the respective controllers are inputted to the respective controlled systems, and deciding on the integral arithmetic results that the respective controllers employ. CONSTITUTION:The multiplexing controller has the triplex constitution of controllers 2-4, and the output signal of one of the controllers 2-4 is selected by a signal selecting circuit 5 and inputted to a controlled system 6. The controllers 2-4 input a setting signal SS inputted to a terminal 1 and a process signal PS outputted from the system 6 to perform integral arithmetic. Coincidence decision circuits 201-20n input output signals outputted from circits 51-5n to systems 61-6n and the output signals of the controllers 2-4 corresponding to the systems 61-6n to decide which controller's output signal is outputted to the systems 61-6n from the circuits 51-5n. The controllers 2-4 send the integral arithmetic results of the respective systems 61-6n through transmission parts 15, 16, and 18 and they are stored. Thus, the high-speed processing is performed.
申请公布号 JPH0475521(B2) 申请公布日期 1992.12.01
申请号 JP19840100552 申请日期 1984.05.21
申请人 HITACHI LTD 发明人 ARITA SETSUO;ITO TETSUO;NOGUCHI SEKIKEN;KAMIMURA HIROSHI;KINOSHITA MITSUO;MIZUNO TAKEHIRO
分类号 G05B7/02;G05B9/03 主分类号 G05B7/02
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