| 摘要 |
<p>PURPOSE:To prevent pseudo synchronization state after restoration even when an external clock is interrupted. CONSTITUTION:A clock input interruption detection circuit 11 outputs clock input interruption information 12 when an input of a 1st clock 5a is interrupted and a clock generating circuit 14 outputs a 2nd clock 5b for data rewrite through a selector 13. The 2nd clock 5b is used to rewrite resident data entirely in plural r-bit delay circuits 2-4 which expand an input series data 1 into parallel data and output the result. A synchronization discrimination circuit 8 discriminates the synchronization state through a phase difference between a synchronization pulse 7 detected from a parallel data by a synchronization pulse detection circuit 6 and frame head information 10.</p> |
