| 摘要 |
PURPOSE:To execute precisely a delay test of a path passing through a combinational logic circuit between F/F by making it possible to invert only an output of specified F/F. CONSTITUTION:When an enable input ENB is changed from 0 to 1 in a delay test of a delay measuring path 30, 12-i changes from 0 to 1 and an output of 5-i is inverted. A clock signal is inputted to a clock CLK 17, being delayed by a measuring time (tc) from the enable input ENB. As the result, scan F/F 4-j takes in negation of an output value (b) after the change in the delay measuring path 30, when a delay time (td) of the delay measuring path 30 is shorter than the measuring time (tc). A value of the scan F/F 4-j is read out by a scan- out operation and tested. The delay time (td) can be measured by observing a change in the F/F 4-j with the measuring time (tc) varied. |
