| 摘要 |
The invention comprises a method for the synthesis of a logic circuit by a data processing system in which a plurality of circuit components are examined and are changed in accordance with preestablished rules, and in which timing parameters are estimated for selected circuit locations. Forward timing delays are determined by adding the timing delays associated with the intervening circuit components and media paths between an input terminal or latch component output terminals and successive locations on the signal path. Similarly, a derived budget timing delay constant is calculated by designating a budget or design delay at any location in the circuit and by subtracting timing delays associated with the intervening components between that location and the previous location along the signal path in the reverse direction. The derived budget timing delay constant is subtracted from the forward timing delay at each selected location to derive a timing debt for each selected location. The timing debt can be used as a criterion to determine when the implementation of circuit component should be changed. The timing information is stored in data structures associated with terminals of components and can include data with respect to a multiplicity of designated paths.
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