| 摘要 |
Semiconductor memory device, with a redundancy device preventing the line address access time from delaying the normal mode of operation. By using a mode detection signal produced by detection of the fact that the memory device will or will not be repaired, the line address is forwarded directly without passing through the delay circuit (30) in the normal mode of operation, whereas line address access is delayed in the redundancy mode of operation. For this purpose, a detection circuit (110) produces a signal dependent on the in or out of circuit condition of the fuse (116), a first transfer path (201) transferring the line address placed in buffer memory without delaying it, a second path (202) delaying the said address by means of the delay circuit (30), and a circuit (120) selecting one or the other of the paths as a function of the mode detection signal (MD). … <IMAGE> … |
