发明名称 CLOCK OBSERVING CIRCUIT
摘要 <p>PURPOSE:To make small an operation clock cycle of an entire circuit device by a method wherein clock skew at an external terminal for clock observation of each printed wiring board is reduced to the minimum, in the circuit device constructed of a number of printed wiring boards. CONSTITUTION:In each wiring board 1, clock supply lines 6a to 6e from IC 3 for clock supply to ICs 2a to 2e are made equal in length. The ICs 2a to 2e are provided with clock observation terminals 4a to 4e respectively. Besides, an external terminal 9 from the IC 3 is provided in the periphery of the board 1 and a time for clock propagation from the IC 3 to the external terminal 9 is adjusted by a variable delay line 8. By making adjustment by the delay line 8 so that a clock signal of the external terminal 9 may have such a phase as to coincide substantially with the midpoint of the maximum of a clock phase shift at each observation terminal, clock skew of each wiring board becomes minimum and a clock cycle of an entire circuit device can be made small.</p>
申请公布号 JPH04340485(A) 申请公布日期 1992.11.26
申请号 JP19910141123 申请日期 1991.05.16
申请人 NEC CORP 发明人 OMAE KENICHI;ISHIZUKI HITOSHI
分类号 G01R31/28;G06F1/04;G06F1/10;H03K5/13 主分类号 G01R31/28
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