| 摘要 |
PURPOSE:To reduce the number of comparators greatly and to perform high-speed, high-resolution A/D conversion by determining the low-order digit bits according to variation in binary number outputted by a digital circuit applied with pulses of prescribed amplitude. CONSTITUTION:Line a1 of decoder 14 is placed in an on-state, and then output voltage Va of sample holding device 2 is applied to A/D converters 4 and 5 and held in latch 6. Next, when line a2 turns on, pulses of constant amplitude R/2 from pulse generator 18 are applied to terminals (p) and p' of pulse device 3 and added to voltage Va to obtain an m-bit binary number that corresponds to the output of converter 5. When this least significant digit bit and the previous least significant digit bit of latch 6 are OR-elseed 8, device 8 generates an output of ''1'' or ''0'' depending upon the exitence of a jump and at the output side of latch 9, bit b1 following the high-order (m) bits is set up. In accordance with ''1'' or ''0'' of bit 9, pulse generator 19 or 20 is triggered to apply a pulse of amplitude R/4 or 3/4R to terminals p and p' of device 3, so that the least significant digit bit b0 is set to the output of latch 10. |
