| 摘要 |
<p>PURPOSE:To perform the peripheral operation without waiting for the processing of a CPU at the time of accessing a memory by a peripheral device by providing the CPU, memories, and the peripheral device and connecting data busses from memories independently of each other. CONSTITUTION:An instruction bus 46 and a first data bus 44 connected to an instruction memory 47 are connected to a CPU 41, and the bus 44 and a second data bus 45 are connected to a data memory 42, and the bus 45 is connected to a peripheral circuit 43. Data is transferred between the peripheral circuit 43 and the data memory 42 through the bus 45 in the period when the CPU 41 does not access the data memory 42 in the instruction cycle of the CPU 41. Preferably, this period is the period privately provided in the instruction cycle or the period of an instruction which does not access the data memory 42.</p> |
