| 摘要 |
<p>An MIS type semiconductor device, in which a source diffusion layer and a drain diffusion layer are formed under the surface of a semiconductor substrate, and a plurality of gate insulation films are formed on the surface of the semiconductor substrate. Further, in the semiconductor device, a plurality of gate electrodes are formed on the plurality of gate insulation films in such a manner to be arranged in series with one another between the source diffusion layer and the drain diffusion layer. Moreover, inter-gate-electrode diffusion layers are formed under the surfaces of regions of the semiconductor substrate among the plurality of the gate electrodes. Furthermore, a conductive layer for covering at least one of the inter-gate-electrode diffusion layers among the plurality of the gate electrodes arranged in series with one another. Thus at least one of the inter-gate-electrode diffusion layers provided among the plurality of the gate electrodes, which are arranged in series with one another and used in a memory cell, is covered by a conductive layer. As the result, the transconductance of an enhancement type transistor can be increased. The characteristics such as an amplification factor and a switching speed of the enhancement type transistor can be improved. Consequently, a high-speed operation can stably be performed. <IMAGE></p> |
