| 摘要 |
<p>The system comprises: a system bus (1) for carrying address, data and control signals; at least one connector (3, 4, 5) for connecting an additional component (e.g. an expansion card) to the system bus (1), the connector (3, 4, 5) being arranged to provide a feedback signal (FS3, FS4, FS5) when the additional component is addressed; and bus control means (2, 6) for controlling the timing of signals carried by the system bus (1) and being responsive to the feedback signal (FS3, FS4, FS5) to alter the bus timings by the insertion of recovery delays between successive bus cycles when the feedback signal (FS3, FS4, FS5) is received. <IMAGE></p> |
