| 摘要 |
PURPOSE:To provide a method for manufacturing to flatten a surface of an interlayer insulating layer covering a surface of a DRAM including a memory cell region and a peripheral region. CONSTITUTION:In a memory cell array including a stacked capacitor 6, a surface of an interlayer insulating layer 23 is formed higher than a peripheral circuit region 4 including a MOS transistor 5. Accordingly, a mask layer for etching is formed on the layer 23 of the region 4 formed at a lower position on a substrate 1, and only the surface of the insulating layer of the region 3 is etched to reduce a thickness of the layer 23. Thus, the surface of the layer 23 between the array and the region 4 is flattened. |
