| 摘要 |
PURPOSE:To reduce a waiting time being a frequency setting time to a negligible degree by driving individually and sequentially plural PLLs so as to set a transmission/reception frequency continuously. CONSTITUTION:A CPU 1 sends a 10ch setting data (a 1st setting data) to a 1st PLL 2a and sends a PLL selective signal to the selector 3 so that the output of the selector 3 is an output from the 1st PLL 2a thereby, awaiting channel setting of the 1st PLL 2a. On the other hand, 1ch, 2ch used succeedingly are respectively set to 2nd and 3rd PLLs 2b, 2c for a time till the channel setting of the 1st PLL 2a is finished. That is, a 1ch setting data being a 2nd setting data and a 2ch setting data being a 3rd setting data are set respectively to the 2nd PLL 2b and 3rd PLLs 2b, 2c being 1ch, 2ch channel setting data. |
