A GATE-TO-DRAIN OVERLAPPED MOS TRANSISTOR FABRICATION PROCESS AND STRUCTURE THEREOF

摘要

The invention relates to MOS transistors in integrated semiconductor devices. There is disclosed a method for fabricating a gate-to-drain overlapped MOS transistor having a lower gate-to-drain capacitance, and a structure of such a transistor. A pad oxide layer (27b) is formed over a substrate (15) having a first conductive layer (23) with a first pattern formed on a first gate oxide layer (17). An etchback process is performed until a surface part and predetermined parts of the both side walls of the first conductive layer are exposed. Then a second conductive layer (33) with a second pattern is formed in contact with the first conductive layer. This second conductive layer overlaps the source and drain of the transistor and lies over a thicker oxide layer (43) than the first conductive layer (23).