发明名称 |
LOGIC PERFORMANCE VERIFICATION AND TRANSITION FAULT DETECTION |
摘要 |
In scan testing of logic parts, this invention provides an inexpensive transition fault test by changing the sequence of application of the A/C and B clocks. In each machine test cycle the B clock is triggered first, and the A/C clock is triggered second. The periodicity of the clocks is not changed for a particular cycle, because in one cycle the B-to-A/C clocking that naturally occurs provides a minimum test window TP for performance and transition fault testing. Thus, less sophisticated scan test equipment can now provide both transition fault and stuck fault testing, without an increase in complexity or expense. BU9-87-035 |
申请公布号 |
CA1310695(C) |
申请公布日期 |
1992.11.24 |
申请号 |
CA19890613497 |
申请日期 |
1989.09.27 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CORR, JAMES L.;VINCENT, BRIAN J. |
分类号 |
G01R31/317;G01R31/3185;G06F11/22 |
主分类号 |
G01R31/317 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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