| 摘要 |
PURPOSE:To speed up memory operations by improving the parasitic capacitance, which is increasing, between bit lines with the reduction of the size of cells and to obtain a high degree of integration for the memory cells by placing bit lines exceeding the gap limit between bit lines. CONSTITUTION:Memory cells M1.1, M1.2... are placed in a matrix manner and bit lines BL1, BL2... are laid down in a column direction. And, among these memory cells, the memory cells, which are located right next to each other in the row direction, use a common bit line. This common use of bit lines make it possible to reduce the number of bit lines by half and to provide an allowance for the bit line pitch. Among the memory cells, which are located next to each other in the row direction, no simultaneous access is possible, therefore, different word lines WL1a, WL1b,... are laid down and a one way or another selection is performed. |
