| 摘要 |
PURPOSE:To obtain a cache memory which can make only data corresponding to an abnormal part ineffective without being made entirely ineffective if part of the memory array becomes abnormal. CONSTITUTION:Mask data which masks access data on a 2nd storage device 3 for a 3rd storage device 4 indicating whether or not the access data is effective is stored on a 4th storage device 5. Further, the cache memory device is provided with an AND circuit which ANDs the output values of the 3rd storage device 4 and 4th storage device 5. The mask data is set on the 4th storage device 5 at addresses where abnormality occurs to the 1st storage device 2 and 2nd storage device 3 and when a microprocessor accesses the abnormal address, an access data effectiveness signal 13 is made ineffective to prevent the access data 9 from being used. |
