| 摘要 |
A random access compare array, on an integrated circuit chip is comprised of a plurality of multi-bit comparator circuits. Each comparator circuit is coupled to a respective multi-bit register; and, each comparator circuit is also coupled to an address distribution circuit which receives a compare address and sends the compare address to all of the comparator circuits. A respective match signal is generated by each comparator circuit which indicates when the compare address and the content of the register that is coupled to the comparator are equal. Also, operating in parallel with the generation of the match signals is a match selection circuit which receives a select address and in response passes one match signal to a single output pin. Due to the parallel operation of the compare-select circuits, the speed of operation is greatly increased; and due to the selective passing of any of the match signals to a single output pin, the size of the array is not pin limited.
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