发明名称 VIDEO SIGNAL CODER
摘要 <p>PURPOSE:To reduce the quantity of arithmetic operation for inter/intra discrimination implemented by an inter/intra selection circuit. CONSTITUTION:The accumulated value of an absolute value of an AC component of a transmission block pattern processing inter data and the accumulated value of an absolute value of an AC component of a transmission block pattern processing intra data are given to a re-conversion coding circuit 14, and the result almost corresponds to a data from an inter/intra selection circuit 12 subjected to conversion coding again. Thus, when the accumulated value of an absolute value of an AC component of the transmission block pattern processing inter data is more than the accumulated value of an absolute value of an AC component of the transmission block pattern processing intra data, the circuit 12 selects a transmission block pattern processing intra data and outputs and terminates the processing. Conversely, when the accumulated value of an absolute value of an AC component of the transmission block pattern processing intra data is more than the accumulated value of an absolute value of an AC component of the transmission block pattern processing inter data, the circuit 12 selects the transmission block pattern processing inter data and outputs and terminates the processing.</p>
申请公布号 JPH04334190(A) 申请公布日期 1992.11.20
申请号 JP19910132114 申请日期 1991.05.09
申请人 SONY CORP 发明人 TAWARA KATSUMI
分类号 H04N19/50;G06T9/00;H04N19/102;H04N19/107;H04N19/126;H04N19/132;H04N19/136;H04N19/14;H04N19/152;H04N19/176;H04N19/186;H04N19/196;H04N19/423;H04N19/46;H04N19/503;H04N19/51;H04N19/587;H04N19/59;H04N19/61;H04N19/625;H04N19/70;H04N19/82;H04N19/85;H04N19/91 主分类号 H04N19/50
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