DECISION SYSTEM OF PACKET SWITCHING TYPE BUS CONTAINING BUS FOR MEMORY COMMON MULTI-PROCESSOR

摘要

PURPOSE: To make a access time, which is limited to a bus, equal and secure to all devices. CONSTITUTION: Clusters 14a-14 consist of one or plural processors 12aa-12ij, and are equipped with local buses 15a-15j which are arbitrated through cache memories 16aa-16ij and switched with packets. The cache memories 16aa-16ij and 19a-19i are constituted in tree structure. A main memory 13 is connected to a global bus 26 through a controller, but the processors 12aa-12ij and I/O devices can be connected to the bus at an arbitrary level of hierarchy. The buses 15a-15i and 26 are arbitrated by arbitrating means 35a-35i and 36 and multiply the buses 15a-15i and 26 in conflicting devices with time at arbitrary points of time to secure equal access to the host bus for each of the devices.