| 摘要 |
<p>A sample-and-hold circuit is provided with a plurality of first capacitors (C1,C2,...,Cn), respectively connected to a plurality of input signal lines through respective first analog switches (S1,S2,...,Sn), for sampling input signal voltages, a plurality of second capacitors (D1,D2,...,Dn), respectively connected to the plurality of first capacitors through respective second analog switches (H1,H2,...,Hn), for holding the sampled voltages, and a single operational amplifier (OPA) for selectively receiving one of the voltages held in the plurality of second capacitors according to a control signal (CNi) supplied thereto, and amplifying and outputting the received voltage. <IMAGE></p> |
