| 摘要 |
A method for fabricating a DRAM cell having enhanced-capacitance attributable to the use of a porous structured polycrystalline silicon layer storage node capacitor plate 68. The present invention is particularly applicable to DRAM cells which employ a stacked capacitor design. Such designs generally employ a conductively-doped polycrystalline silicon layer as the storage node capacitor plate 68, or lower capacitor plate. A microstructure is formed by anodizing the storage node plate layer in a solution of hydrofluoric acid to produce microstructures 63 resembling elongated pores in the storage node capacitor plate 68 plate. The elongated pores are texturized to produce three-dimensional asperities 66 that further increase surface area of the storage node capacitor plate 68. This is followed by the deposition of a thin conformal (typically less than 100 Angstroms) silicon nitride layer 69 which in turn is followed by the deposition of a second poly-crystalline silicon (poly) layer 70, which functions as the capacitor field plate 73. Since the nitride layer 69 is thin in comparison to the texturized elongated pores in the storage node plate layer, capacitive area is substantially augmented. Cell capacitance can be increased by more than 1,000 percent using the storage node capacitor plate 68 having microstructures 63 thus formed. <IMAGE>
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