| 摘要 |
<p>PURPOSE:To provide a read-only semiconductor memory device which can remarkably improve the defective bit remedying rate. CONSTITUTION:A plurality of address coincidence detection circuits (9-1)-(9-k) to which specific areas are respectively assigned and generate address coincidence detect signals when an input address signal designates an address in their assigned areas are provided. When output coincidence detect signals are outputted from the plurality of coincidence detection circuits, a priority circuit 20 decides the priority order of each signal. According to the signals to which priority order is decided by the circuit 20, the logical level of a data output terminal 11 is set to memory cell data read out from a memory array 5 or fixed to a prefixed logical level. For memory areas where logic '1' or '0' continues, the data of the prefixed logical level are outputted to the data output terminal by means of a switching circuit. Since data separated from the memory array are outputted to the continuous areas, a defective bit in the continuous areas can be efficiently remedied and the yield of this read-only semiconductor memory device can be improved.</p> |
