| 摘要 |
PURPOSE:To eliminate the necessity of increasing the number of circuit elements when a count value is increased and to simplify the configuration of a circuit by dividing data to be counted into plural blocks and processing plural divided block data. CONSTITUTION:In the case of data consisting of 16 bits e.g. as a count value, the data are divided into two, i.e., upper and lower, blocks each of which consists of 8 bits by a channel corresponding address (1) and an address bit (2) and then the lower 8-bit data are outputted (3). The adding processing of the output data is executed by an adder 4, a latch circuit 5 and an integration memory 1. Similar adding processing is applied to the upper 8-bit data by the address bit (2). Since '1' is added to the 16-bit data in each processing out of twice the adding processing, the adder 4 and the latch circuit 5 having only 8-bit constitution can process 16-bit data. Consequently the configuration of the circuit can be simplified and the cost of this multi-channel analyzer can sharply be reduced.
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