| 摘要 |
<p>A processor including an instruction register which holds a plurality of user instruction codes one by one, a state counter which outputs a number indicating the internal state of a system which changes along with the execution of instructions, and a decoder which receives as input the contents of the instruction register and the state counter and produces various types of control signals for the system. The processor has two further units added. One is a detection/storage unit which detects the occurrence of predetermined specific processing and when detecting the same stores the specific instruction code preselected from among the abovementioned user instruction codes in the instruction register. The other is a state changing unit which, when there is a detection, presets the internal state number shown by the state counter to a certain value by force and which converts the instruction corresponding to the specific instruction code to an instruction compatible with the above-mentioned specific processing. <IMAGE></p> |
