| 摘要 |
PURPOSE:To improve operating speed by constituting a multiplier for the mantissa part of a signed binary adder tree and a subtractor and finding out the total logical sum of cut-off bits from the output of the signed binary adder. CONSTITUTION:The exponential parts E1, E2 of a floating decimal point segmented in the preprocessing stage are mutually added by an exponential part adder 1. The mantissa parts M1, M2 consisting of (n) bits in the floating decimal point are multiplied by each other by a multiplier 2. The total OR H of outputs D, F respectively corresponding to about lower (n) bits of each of the outputs B, C of the signed binary adder tree 21 is found out by an OR circuit 3. A rounding digit positioning device 4 outputs the output I of the floating decimal point multiplier based upon the output A of the adder 1 and the upper bits G of the output of the multiplier 2 by using the total OR H as a control signal. Since total delay time = preprocessing + multiplication + rounding digit positioning is formed, the operation time can be shortened only by the calculation time of the total OR. |
