SCHALTUNGSANORDNUNG ZUR ABTASTUNG EINES TERNAEREN SIGNALES.

摘要

The outputs of the comparators are scanned with a clock at M times the symbol frequency and phase-locked to it. The scanned values are shifted through registers with at least M stages and transferred to intermediate stores at the symbol frequency. A logic circuit, comprising paired AND-gates, processes the values to outputs corresp. to groups of sequential store positions. A binary 1 exists on the outputs if one of the groups contains only binary 1s, and causes a counter to increment. A binary 1 is written into a third intermediate store when the counter stages reach binary 1 and the counters are reset when a higher count is reached. The intermediate storeis connected to a selection circuit which outputs only one of the supplied binary 1s.With the signals at the output of the selection circuit a gate circuit feeds through one of the binary scanned Values stored in the first and second intermediate stores.