| 摘要 |
PURPOSE:To improve the resolution of a vertical synchronizing signal, at the time of operating a countdown processing. CONSTITUTION:The vertical synchronizing signal from a synchronizing separator circuit 41 is supplied to a vertical synchronizing processing circuit 100, a horizontal synchronizing signal is supplied to a multiplying circuit 42, and a multiplied 2fH signal is supplied to the vertical synchronizing processing circuit 100 and a deflection correction waveform generating circuit 200. Then, a count value (X) counted by the vertical synchronizing processing circuit 100 is supplied through a register 300 to the deflection correction waveform generating circuit 200, and it is outputted as a desired correction waveform(YSAW and YPARA) or the like. And also, the multiplied 2fH and 4fH signals are respectively supplied to latch circuits 43 and 44, the vertical synchronizing signal from the synchronizing separator circuit 41 is supplied to those latch circuits 43 and 44, and the 2fH and 4fH signals are latched in the timing of the vertical synchronizing signal. The latched signals are supplied to the register 300. |
