| 摘要 |
A transition signalling communication system suitable for use in a high speed data communication bus between a bus master (12) and two or more peripheral slave devices (14) provides data transfer rates up to twice the maximum clock frequency. The bus architecture permits transition signalling to be used with a plurality of slave devices with tri-state or open collector control signals. The bus master (12) includes a first control signal (REQ), which initiates a data transfer request by the transition of said first control signal, and a second control signal (REQINVALID) which provides an indication whether said first control signal transition is valid. In response, the slave includes a third control signal (ACK) which acknowledges the first control signal by the transition of said third control, and fourth control signal (ACKINVALID) which provides an indication whether the third control signal transition is valid. <IMAGE>
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