发明名称 MONITOR AND CONTROL SYSTEM
摘要 <p>PURPOSE:To reduce the power consumption of a processor in a monitor and control system for monitoring a transmitter, an exchange, and so on. CONSTITUTION:The monitor and control system is provided with a control circuit 2 for resetting a processor 1 and releasing the reset, a self-monitoring part 3 for adding test data to a prescribed monitoring block and monitoring the block and a decoding part 4 for decoding error detection data outputted from the self-monitoring part 3. When the decoding part 4 decodes the error detection data indicating the existence of an error in the self-monitoring part 3 after turning the processor to an aborted state by resetting, the control circuit 2 releases the reset of the processor 1 to an operating state and adds the error detection data to the processor 1 to process the error detection data by the processor 1.</p>
申请公布号 JPH04332054(A) 申请公布日期 1992.11.19
申请号 JP19910101312 申请日期 1991.05.07
申请人 FUJITSU LTD 发明人 NANBA KENSABURO;TANIGUCHI MITSUKI
分类号 G06F1/32;G06F1/26;G06F11/30 主分类号 G06F1/32
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