Register file for bit slice processor with simultaneous accessing of plural memory array cells

摘要

A register file for a bit slice ALU includes a static RAM array (86) which is addressable by two input read addresses. The addresses decoded by decoders (104) and (106) for input to the array (86). The array (86) simultaneously outputs two data words in response to two read addresses to sense amps (94) and (98). Data can be written into the memory by storing it in a data latch (100) and addressing it with a separate write address. The separate write address is latched in a write address (108) which is enabled on the rising clock edge by control circuit (114).