| 摘要 |
<p>An address pattern generator (10) generates an address pattern which successively specifies the X-Y addresses of each memory cell of a semiconductor memory device (14) which is to be tested. An address changeover part (11) accesses the semiconductor memory device (14) with the address pattern supplied by the address pattern generator (10) in a normal mode, and accesses the semiconductor memory (14) with an address pattern supplied by the address pattern generator (10) in which predetermined addresses are interchanged in a swap mode. A comparator (13) compares data read-out from the semiconductor memory device (14) with an expected value to detect hardware error, and a fail memory device (12) stores information concerning the existence or non-existence of hardware error in each of the memory cells of the semiconductor memory device (14) into an address region corresponding to that of the semiconductor memory device (14). The semiconductor memory device (14) and the fail memory device (12) both receive common X-Y addresses from the address changeover part (11). The comparator (13) is inhibited in its comparing operation by a signal supplied from said fail memory device (12) for the memory cells of the semiconductor memory device (14) corresponding to the memory cells of the fail memory device (12) which have information stored therein indicating the existence of hardware errors. </p> |
