发明名称 BIT INTERLEAVED PARITY ARITHMETIC CIRCUIT
摘要 PURPOSE:To reduce number of signal lines, to simplify the circuit constitution and to save number of pins in the case of large scale circuit integration, in the case of digital transmission. CONSTITUTION:A B1 (B3) calculation circuit 10 applies parity arithmetic operation to an 8-bit input signal. A P/S conversion circuit 11 converts the result of 8-bit calculation into a serial signal and a 1-bit parity arithmetic circuit 12 applies parity arithmetic operation to a serial signal whose low-order level is transferred one by one bit. The result of arithmetic operation is transferred one by one bit each and an S/P conversion circuit 13 is used to restore the signal into an 8-bit signal and the result is fetched in a register 14.
申请公布号 JPH04322530(A) 申请公布日期 1992.11.12
申请号 JP19910090358 申请日期 1991.04.22
申请人 MATSUSHITA ELECTRIC IND CO LTD;NIPPON TELEGR & TELEPH CORP <NTT> 发明人 TOMOTA MASAAKI;MATSUMOTO KOJIRO;OKUMURA YASUYUKI;KISHIMOTO RYOZO
分类号 G06F11/10;H03M9/00;H03M13/00;H04J3/00;H04L1/00 主分类号 G06F11/10
代理机构 代理人
主权项
地址