| 摘要 |
PURPOSE:To present a cache memory capable of increasing the speed of access from the external and parity error recovery by performing the parity check at a high speed. CONSTITUTION:The parity check is performed as the retrieval processing using the parity generated from a virtual address by a parity generating circuit 12, and the retrieval processing is performed by the physical address in the case of a mis-retrieval. In the case of success in retrieval, the virtual address tag of the pertinent entry is updated, and the physical address tag read out from the entry is used to perform the parity check of the physical address; and if parity error occurs, the entry where the parity error occurs is updated by the physical address obtained by conversion of the virtual address generated from the virtual address tag of the entry. |
