| 摘要 |
A memory system (10) for use with a processor (12) which provides a memory bus (14) and an address bus (38). The inventive system includes a plurality of mostly good memory blocks (21-36) connected to the address bus (38), each block having a defect at a defect address. A programmable memory (PROMs A and B) is connected to the processor memory bus (14) for storing the addresses of the defects in the mostly good memories (21-36). A redundant memory (42 and 44) provides rows and columns of good memory at addresses corresponding to the addresses of the defects in the mostly good memories (21-36). A selector controller (40) selectively activates the redundant memory when an address is placed on the memory bus (14) which corresponds to an address of a defect in one of the mostly good memories (21-36). |
