| 摘要 |
A digital data synchronizer, synchronizes a digital data system to an incoming serial bit stream having a segment of pseudo random bit sequence, which is a function of a predetermined primitive polynomial, preceeding the start of data. The synchronizer includes a first feedback shift register configured as a multiplier for generating the pseudo random bit sequence. The multiplier register operates on the incoming serial bit stream to determine whether a valid bit sequence of the primitive polynomial is present in the incoming serial bit stream, and if it is, a zero output is produced. A second feedback shift register configured as a divider produces a pseudo random bit sequence which is also a function of the predetermined primitive polynomial. A counter is provided to monitor the number of zeros outputted by the multiplier feedback shift register. When a preset count is reached, the contents of the multiplier shift register is parallel loaded into the divider shift register if the bit sequence of the divider shift register does not match the bit sequence of the incoming serial data. Thus, the divider pseudo random sequence is synchronized to the incoming serial data. A synch word detector monitors the parallel contents of the divider register. When the synch word detector detects a predetermined word in the pseudo random bit sequence produced by the divider, it produces an output flag which indicates the next bit in the incoming digital data word is the first data bit.
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