| 摘要 |
A Bit Error Rate (BER) test arrangement, composed of two autonomous BER test systems, effects the full-duplex testing of a pair of co-located modems terminating a simulated transmission link by utilizing a single processor to control each independent BER test system and a buffer storage device, preferably a dual-port random access memory and a multiple access memory serving each of the test systems, to post information communicated between the controller processor and each of the test systems. This arrangement minimizes duplication of circuitry by assigning basically identical processing operations of the individual test systems to the single processor.
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