| 摘要 |
In a communication bus system all data is echoed by a common echo buffer station on a first bilevel unidirectional element or wire, in the form of sequential selfclocked bivalent information packets. Peripheral stations have clock extraction provisions for clocked interrogation of those packets, absorbing the information if required, and thereupon transmitting a self-determined non-selfclocked binary information value on a second bilevel unidirectional element or wire that has a wired-logic functionality (wired-OR, wired-AND) so that coexistently transmitting peripheral stations may be subjected to arbiter operation. A peripheral station may have clock extraction means and transfer the extracted clock on a third wire, in parallel with unclocked data on a fourth wire, third and fourth wire in parallel feeding a plurality of access modules. Any access module may then feed a fifth wire with its data, all fifth wires in parallel feeding the second wire via associated bridge elements.
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