| 摘要 |
A discrete cosine transforming apparatus for exercising a 2n+1th order discrete cosine transform includes a plurality of basic arithmetic circuits A including circuits for temporarily storing input data and adding the input data or subtracting the input data one from the other, and a plurality of another basic arithmetic circuits B including circuits for temporarily storing input data and adding the input data or subtracting the multiplication result data obtained by multiplying the sum or subtraction result by a multiplier that is equal to or less than the input data. The basic arithmetic circuit A is located at a first stage, and then the basic arithmetic circuit B and the arithmetic circuit A are alternately arranged, thereby to form a cascade connection of "n" stages. For the inverse transform, the same circuit arrangement as that for the cosine transform is used and the direction of a signal flow is inversed.
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