| 摘要 |
PURPOSE: To provide a data edge phase discriminating circuit for a communication system, an information processing system and a data-processing system using a digital phase-locked logic circuit. CONSTITUTION: This discrimination circuit discriminates an edge phase of a consecutive data DATA stream corresponding to a local clock signal. The local clock signal is coupled with a delay line 56, having a plurality of continuously connected delay elements, and delayed clocks with a different phase are outputted. The discrimination circuit includes an extracting circuit coupled therewith, that detects transition of an edge in the consecutive data DATA stream and receives the consecutive data DATA stream to output a pulse for a preset time corresponding to each detected transition. A circuit coupled with the extraction circuit is a non-consecutive state discrimination logic circuit 54, which receives a local clock 58 via the delay line 56. The non-consecutive state discrimination logic circuit 54 receives a pulse and a plurality of delayed clocks of the extracting circuit outputted, to discriminate the pulse in response to the delayed clock. |
