| 摘要 |
PURPOSE:To obtain a timer input controlling circuit which does not confuse count value because of no generation of whisker shape pulse by making output signal of an SR flip-flop(FF) the signal having delay greater enough than clock pulse width for counting operation. CONSTITUTION:Timer input signal 3 is led to a data D input of a transparent latch 7 having a direct reset. Also, an SRFF has three inputs, and, to the first S1 input, reverse signal of a counter write-in signal is input, to the second S2 input, permit/forbid signal 2 is input, finally to an R input, the signal 3 is input, and outputs thereof is led to a G input of the latch 7. A gated delay circuit 11 makes the output signal of the SRFF 4 to be signal having delay greater enough than clock pulse width for counting operation, obtains logical sum of the signal and a system clock 1 and logical product of the signal and the counter write-in signal, in order to lead to the direct reset R input of the latch 7. In this way, no whisker shape pulse is generated and therewith the count value is never confused. |
