发明名称 TDMA TRANSFER SYNCHRONIZING CIRCUIT AND TDMA EQUIPMENT
摘要 <p>PURPOSE:To obtain a TDMA transfer synchronizing circuit in which the synchronization of transfer is accurately established with simple constitution and to realize the TDMA equipment having an elastic buffer capable of re-reading with a clock signal without fluctuation with the accurate transfer synchronization. CONSTITUTION:The TDMA transfer synchronizing circuit 24 is provided with a re-timing circuit 31 synchronizing a synchronization word detection signal S5 detected by a burst reception signal S1 with a system clock S4 having a frequency being (n) times of the frequency of the reception signal S1 and with a frequency divider 32 cleared by the synchronization word detection signal S5 subjected to re-timing and applying 1/n frequency division to the system clock S4. The output S6 of the frequency divider 32 is used for a transfer timing signal of its own station. Furthermore, the TDMA equipment is provided with the above-mentioned TDMA transfer synchronizing circuit 24 and an input and output asynchronizing memory 26 in which a burst reception signal is written, and the output of the frequency divider 32 is used for the read clock of the input and output asynchronizing memory 26.</p>
申请公布号 JPH04320125(A) 申请公布日期 1992.11.10
申请号 JP19910088700 申请日期 1991.04.19
申请人 SHARP CORP 发明人 UCHIYAMA AKIHIKO
分类号 H04J3/00;H04J3/06;H04L7/04;H04L7/08 主分类号 H04J3/00
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