发明名称 FRAME ALIGNING CIRCUIT
摘要 PURPOSE:To easily detect a frame aligning signal having an optional bit pattern by comparing a stored reception data with a prescribed bit pattern while shifting the data one by one bit or reading the bit of a succeeding row. CONSTITUTION:When a received data is serially inputted one by one bit from an input terminal IN, the data is stored in a memory 3 via a selector 2 by using a control signal 61. Then an 8-bit data read from the memory 3 and stored in a register 1 is imparted to the input A of a comparator 4. The data and a fixed bit pattern stored in advance in a shift register 5 and imparted to an input B are compared and when each bit of them is coincident, a coincidence signal is outputted from a terminal A=B to a terminal OUT via a control circuit 6 to establish frame synchronization. When they are discordant, the bit pattern of the register 5 is shifted by one bit and the result is compared with the data again, and when not coincident further, a 1-bit received next is stored in the memory 3, a succeeding column is read from the register 1 by using a control signal 62 and imparted to the input A for the comparison.
申请公布号 JPH04318719(A) 申请公布日期 1992.11.10
申请号 JP19910086394 申请日期 1991.04.18
申请人 MURATA MACH LTD 发明人 IMOTO KUNIO
分类号 H04L7/08 主分类号 H04L7/08
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