发明名称 RESET CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To increase the number of decodable test conditions and shorten testing time without increasing the number of test terminals for controlling a test circuit and, at the same time, to simplify the hardware and software required at the time of performing tests and improve the probability of the tests. CONSTITUTION:A rise and fall detection circuit EDGE detects the changing point of a reset pulse by distinguishing whether the point is a rising or falling point. A timer counter circuit COUNT stops its counting operation when a counter stop signal STOP8 given from a timer counter control circuit CONT rises and measures the width of the low-level period of the reset pulse. A test signal TEST1 rises to a high level only when the width of the low-level period of the measured reset pulse coincides with the low-level period of the reset pulse stored in a register circuit MEM1 and the timer counter circuit COUNT is stopped due to the rise of the reset pulse.
申请公布号 JPH04316136(A) 申请公布日期 1992.11.06
申请号 JP19910082790 申请日期 1991.04.16
申请人 NEC CORP 发明人 HIRAYAMA TAKESHI
分类号 G06F1/24;G06F11/22;G06F15/78 主分类号 G06F1/24
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