| 摘要 |
PURPOSE:To prevent the lock of a clock for regenerating from stepping out and to enable re-pull-in by controlling a selecting circuit or a PLL circuit based on a dropout detecting signal or a synchronizing step-out detecting signal. CONSTITUTION:When a device is operated in a reading mode and an encoding data is signal processed, the output of an OR circuit 8 is in an active state with a logic 'H' when the dropout or the synchronizing step-out is generated. Then, at this time, by a switch circuit 3, a signal S1 frequency dividing a system clock is selected and by the switch circuit 5, the signal S2 frequency dividing a VCO clock is selected respectively. Thus, by the PLL circuit 6, PLL loop is switched so that a system clock is followed up by the VCO clock. Therefore, when the dropout or the synchronizing step-out is generated while processing to regenerate, no VCO clock is stepped out from a locked state, further, if the synchronization is stepped out, the re-pull-in is performed rapidly. |
