| 摘要 |
<p>PURPOSE:To improve the speed and capacity of a switch by providing memory buffers by priority classes for each incoming line, transmitting a cell having a queue reaching a threshold value and a cell having a lot of times for waiting, and setting an interval for cell transmission. CONSTITUTION:An access unit(AU) 101 constituting the ATM switch and a bus controller(BC) 102 are connected by a data bus 103 for transmitting cells and a control bus 104 for exchanging control signals to decide the AU 101 to transmit the cell to the bus 103. The bus 103 transfers cells parallelly with 16 bits, and the bus 104 is composed of signal lines for transmitting a transmission request for each AU 101, two priority classes, threshold value over and interrupting signals. The cell is transmitted to the bus 103 by the AU 101 possessing the cell priority right, when receiving the cell, all the AU 101 fetch the cells on the bus 103, when the cell is addressed to the other AU, it is abandonned and when the cell is addressed to its own AU, it is received.</p> |
