| 摘要 |
<p>PURPOSE:To improve the performance of a computer system by detecting the idling state of a CPU with hardware. CONSTITUTION:An instruction decoding circuit 4 decodes an idling instruction which is read out by a CPU 1 from a memory 2 and sets the CPU 1 to an idling state and a counter 6 counts the number of reading-out times of the instruction. A timer 7 starts the measurement of time when the counter 6 makes the first counting and, at the same time, initializes the counter 6 after the elapse of certain fixed time. A counter value comparison circuit 8 sends the idling state informing signal of the CPU when the value of the counter 6 reaches a certain set value within the fixed time of the timer 7. When the idling state informing signal is sent, the system incorporating the CPU detects the idling state of the CPU and, therefore, the system can efficiently perform the downing or stopping of an operation clock, actuation of a power consumption reduction circuit, or interrupting operation to the CPU.</p> |
