SYNCHRONOUS SEMICONDUCTOR MEMORY.

摘要

A dynamic random access memory capable of controlling the output timing of read data, which comprises a circuit (127) for counting clock pulses until the read data is transferred to a data latching circuit (121), and a circuit (129) for outputting the counted value to an external unit, so as to make it possible to control the output timing. Moreover, the dynamic random access memory is provided with a circuit (125) capable of controlling the output timing by an external input signal.